1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including an array configuration suitable for attaining lower power consumption.
2. Description of the Background Art
In order to enhance operation characteristics and layout efficiency of a semiconductor memory device so as to adapt to drive with a lower voltage for attaining lower power consumption, an array configuration in which a configuration of an internal power supply system or a circuit configuration of a peripheral circuit is devised is disclosed, for example, in Japanese Patent Laying-Open Nos. 8-55480, 2000-21170, and 9-198867.
In recent years particularly, a semiconductor memory device attaining a smaller size and lower power consumption is further strongly demanded, considering mount on a portable instrument or the like premised on drive by a battery. Accordingly, a transistor (represented by an MOS (Metal Oxide Semiconductor) transistor) disposed on the semiconductor memory device has come to achieve a smaller size and a lower threshold voltage. Under such circumstances, aiming to achieve a stabilized operation under low voltage drive as well as optimal design of a power supply system, further improvement in the array configuration has been demanded.